FPGA Based Implementation of Symmetrical Switching in SVPWM for Three Level NPC Converter

This paper presents the FPGA based implementation of symmetrical switching strategy in SVPWM for three level NPC converter. A simplified switching strategy is proposed by exploiting the redundant states of switching vectors available in three level space vector resulting into symmetrical switching sequence. This switching strategy leads to generate switching sequence for all regions of every sector with each switch has to be turned “ON’ once in time period resulting into lower device stress and reduced switching loss. The proposed switching strategy is developed using FPGA based Xilinx block sets and tested on hardware test bench consists of Induction motor integrated to the three level Neutral Point Clamped (NPC) converter controlled by FPGA based wavect controller. It is observed from the results, that the complexity of SVPWM for three level inverter is reduced to that of two level inverter and address the problem of narrow pulse width at the midpoint of NPC converter