改进了任意输入数的奇偶归并排序网络

C. J. Kuo, Zhi W. Huang
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引用次数: 13

摘要

本文提出了一种改进的网络结构,可以对任意大小的数据进行排序。所提出的VLSI架构是直接从Batcher的奇偶合并排序网络改进而来的。该体系结构的主要优点是采用模块化方法、简单而规则的互连以及易于通过VLSI技术实现。
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Modified odd-even merge-sort network for arbitrary number of inputs
Modified network architecture for sorting data of any size is presented in this paper. The proposed VLSI archi- tecture is directly modified from the Batcher's odd-even merge-sort network. The major advantage of the proposed architecture is its modular approach, simple and regular interconnection and easy implementation by VLSI technol- ogy.
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