High Signal Integrity Transmission Line Using Microchip Capacitors and its Design Methodology

In the high-speed data transmissions in GHz domain,such as PCIe (Gen.5) and USB 5.0, slight impedance mismatching caused by via-holes and/or through-holes, or other small parasiticelements in the traces in printed circuit board (PCBs) causes serious deterioration of signal integrity (SI). And it is becoming next to impossible to ensure the SI by using the conventional impedance matching techniques as the frequency increases. In order toovercome this problem, we propose a novel high signal integrity transmission line structure called “Capacitor Segmental Transmission Line (C-STL)”. The C-STL is a novel signal integrity improving technique that makes use of not the characteristic impedance matching but the mismatching. In the C- STL, we use small microchip capacitors embedded in the PCB under the trace, and superpose the intentional reflections,which cause from the capacitors, onto the target distorted signal waves to restore them to ideal waveforms. In this paper, we also propose the design methodology of the C-STL and demonstrate its effectiveness using simulations and prototype measurements.