A Staggered Nand Dram Array Architecture For A Gbit Scale Integration

Cascade arrangement of DRAM cells, NAND structured DRAM cell, have already been proposed to reduce the cell size[l] and the experimental 256Mbit chip has been fabricated to demonstrate a small chip size[2]. However, realizing IGbit or further, the NAND DRAM faces a crucial array noise problem due to its open bitline (BL) array arrangement which has larger array noise than the folded BL arrangement[3]. The conventional NAND DRAM inevitably adopts the open BL arrangement, because memory cells are placed a t all the intersection between wordlines and bitlines, so all the BL’s receive the cell data when a wordline is activated, accordingly reference BL’s cannot be arranged in the same memory mat. To overcome this problem, we propose a Staggered NAND DRAM array architecture which realizes folded BL scheme in a NAND DRAM.