微处理器阵列结构的硬故障容忍度

Fred A. Bower, Paul G. Shealy, S. Ozev, Daniel J. Sorin
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引用次数: 104

摘要

在本文中,我们提出了一种硬件技术,称为自修复阵列结构(SRAS),用于掩盖微处理器阵列结构中的硬故障,如重排序缓冲区和分支历史表。SRAS屏蔽了可能导致系统恢复缓慢的错误。为了检测行错误,对一行的每次写入都会镜像到专用的“检查行”。然后我们读出写行和校验行,并比较它们的结果。为了纠正错误,SRAS用一定程度的间接映射出有错误的数组行。
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Tolerating hard faults in microprocessor array structures
In this paper, we present a hardware technique, called self-repairing array structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history table. SRAS masks errors that could otherwise lead to slow system recoveries. To detect row errors, every write to a row is mirrored to a dedicated "check row". We then read out both the written row and check row and compare their results. To correct errors, SRAS maps out faulty array rows with a level of indirection.
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