无线通信标准LDPC解码器体系结构的FPGA实现

R. Goriushkin, P. Nikishkin, E. Likhobabin, V. Vityazev
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引用次数: 1

摘要

本文提出了一种准循环(QC)低密度奇偶校验(LDPC)码的解码器设计。该设计是参数化的,可以很容易地重建,以支持来自WiMAX (IEEE 802.16e)和WiFi (IEEE 802.11n)标准的各种LDPC奇偶校验矩阵。提出了译码结构核心并行化等新技术。这些核心计算变量到检查(VTC)和新的检查到变量(CTV)消息,并更新后验概率(app)。并行多核解码架构意味着基于LDPC矩阵的值的先验移位和核值的同时计算。我们的解码器在Zynq-7000 Mini-ITX评估板(XC7Z100-2FFG900)的fpga上实现。吞吐量可达1.2 GBit/s,工作频率可达240mhz。
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FPGA Implementation of LDPC Decoder Architecture for Wireless Communication Standards
This paper presents a decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. The design is parameterized and can be easily rebuilt to support various LDPC Parity-Check matrices taken from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards. New techniques such as parallelization of the decoding architecture cores are proposed. These cores calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update posterior probabilities (APPs). The parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Our decoder is implemented on FPGAs of the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900). The throughput of up to 1,2 GBit/s and the operation frequency of up to 240 MHz have been achieved.
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