低功耗异构SoC平台51mW 1.6GHz片上网络

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332639

Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi Choi, Donghyun Kim, Sunyoung Kim, Min-wuk Lee, H. Yoo

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引用次数: 104

摘要

1.6GHz片上网络集成了两个处理器、存储器和一个FPGA，采用0.18/spl mu/m 6M CMOS技术，提供11.2GB/s带宽。采用串行低能量传输编码、交叉部分激活和低摆幅信号的2级分层星形连接网络在1.6V时耗散51 mW，支持全局异步、局部同步模式和可编程时钟。

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A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform

A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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