用于外部存储器和互连的板/系统级测试的基于指令的标准

O. Caty, I. Bayraktaroglu, Amitava Majumdar, Richard Lee, J. Bell, L. Curhan
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引用次数: 4

摘要

本文描述了一种使用片上逻辑测试外部存储器/缓存和存储器互连的一般技术。这种测试方法有望显著降低电路板系统制造测试成本,并提高内存和内存互连故障的可诊断性。所提出的方法包含了大量的可编程性(包括可编程的MARCH算法和数据背景),以便对当今系统中遇到的所有不同类型的内存和缓存进行适当的测试。该方法的另一个重要方面是它对片上内存缓存控制器的重用。这允许对方法进行调整以适应各种内存访问协议(包括DDR),而不必在BIST引擎内部重新实现访问协议。这些考虑使得论文中提出的外部BIST方法;非常通用,适用于广泛的应用程序及其相应的存储子系统。
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Instruction based bist for board/system level test of external memories and internconnects
This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduce boardhystem manufacturing test cost as well as to improve diagnosability of memory and memory-interconnect failures. The proposed methodology incorporates a significant amount of programmability (including programmable MARCH algorithms and data backgrounds) to enable proper testing of all diflerentjavors of memories and caches that one encounters in systems today. Another important aspect of the methodology is its reuse of on-chip memorykache controllers. This allows the adaptation of the methodology to a variety of memory access protocols (including DDR), without having to re-implement the access protocol inside the BIST engine. These considerations make the External BIST methodology presented in the papei; very general and adaptable to a wide range of applications and their corresponding memory sub-systems.
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