T. Hamada, N. Tanabe, H. Watanabe, K. Takeuchi, N. Kasai, H. Hada, K. Shibahara, K. Tokashiki, K. Nakajima, S. Hirasawa, E. Ikawa, T. Saeki, E. Kakehashi, S. Ohya, T. Kunio
{"title":"用于256mb dram的分级对角位线(SLDB)堆叠电容单元","authors":"T. Hamada, N. Tanabe, H. Watanabe, K. Takeuchi, N. Kasai, H. Hada, K. Shibahara, K. Tokashiki, K. Nakajima, S. Hirasawa, E. Ikawa, T. Saeki, E. Kakehashi, S. Ohya, T. Kunio","doi":"10.1109/IEDM.1992.307478","DOIUrl":null,"url":null,"abstract":"A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell having a cylindrical storage node with hemispherical grained (HSG) silicon is proposed for 256 MbDRAMs. This memory cell provides large alignment tolerance between contact hole and wiring, large word-line noise immunity and large storage capacitance in a small cell area of 0.54 mu m/sup 2/ with 0.25 mu m design rule.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell for 256 Mb DRAMs\",\"authors\":\"T. Hamada, N. Tanabe, H. Watanabe, K. Takeuchi, N. Kasai, H. Hada, K. Shibahara, K. Tokashiki, K. Nakajima, S. Hirasawa, E. Ikawa, T. Saeki, E. Kakehashi, S. Ohya, T. Kunio\",\"doi\":\"10.1109/IEDM.1992.307478\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell having a cylindrical storage node with hemispherical grained (HSG) silicon is proposed for 256 MbDRAMs. This memory cell provides large alignment tolerance between contact hole and wiring, large word-line noise immunity and large storage capacitance in a small cell area of 0.54 mu m/sup 2/ with 0.25 mu m design rule.<<ETX>>\",\"PeriodicalId\":287098,\"journal\":{\"name\":\"1992 International Technical Digest on Electron Devices Meeting\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 International Technical Digest on Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1992.307478\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 International Technical Digest on Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1992.307478","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell for 256 Mb DRAMs
A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell having a cylindrical storage node with hemispherical grained (HSG) silicon is proposed for 256 MbDRAMs. This memory cell provides large alignment tolerance between contact hole and wiring, large word-line noise immunity and large storage capacitance in a small cell area of 0.54 mu m/sup 2/ with 0.25 mu m design rule.<>
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