{"title":"DSP-ASIC的结构与电路设计","authors":"O. Vainio, H. Tenhunen, J. Nurmi","doi":"10.1109/EASIC.1990.207910","DOIUrl":null,"url":null,"abstract":"The two alternative design approaches discussed in this paper are dedicated DSP architectures and the core processor based design methodology. By the development of area-efficient high resolution A/D converters, it has become feasible to integrate the analog interface on the same chip with the DSP operations. However, lack of an interdisciplinary high-level CAE environment tends to lengthen the design times of DSP-ASICs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Architecture and circuit design for DSP-ASIC\",\"authors\":\"O. Vainio, H. Tenhunen, J. Nurmi\",\"doi\":\"10.1109/EASIC.1990.207910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The two alternative design approaches discussed in this paper are dedicated DSP architectures and the core processor based design methodology. By the development of area-efficient high resolution A/D converters, it has become feasible to integrate the analog interface on the same chip with the DSP operations. However, lack of an interdisciplinary high-level CAE environment tends to lengthen the design times of DSP-ASICs.<<ETX>>\",\"PeriodicalId\":205695,\"journal\":{\"name\":\"[Proceedings] EURO ASIC `90\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] EURO ASIC `90\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EASIC.1990.207910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] EURO ASIC `90","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EASIC.1990.207910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The two alternative design approaches discussed in this paper are dedicated DSP architectures and the core processor based design methodology. By the development of area-efficient high resolution A/D converters, it has become feasible to integrate the analog interface on the same chip with the DSP operations. However, lack of an interdisciplinary high-level CAE environment tends to lengthen the design times of DSP-ASICs.<>