A. Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, K. Kishine, H. Onodera
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Impact of on-chip multi-layered inductor on signal and power integrity of underlying power-ground net
This paper discusses power/ground noise induced by on-chip multi-layered inductors. Employing multi-layered inductors instead of spiral inductors is an effective choice for area-efficient bandwidth enhancement. However the impact of the coupling between multi-layered inductors and underlying circuit is still not clear. We evaluate inductive/capacitive coupling and the impact on the power and the signal integrity. Electromagnetic simulation and circuit simulation show that dense power/ground structure makes the impact of coupling small. The peak-to-peak noise voltage becomes less than 5 mV against 1 V aggressor swing.
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