Time-domain computing circuits for addition and multiplication computation

This paper presents an addition and multiplication computation cell using pulse train time amplifier (TA) and time register (TR), which could be easily extend to large-scale computation. The proposed pulse train TA exploits a delay cell ring to realize large input range. In TR a gated delay line with MOS capacitor is adopted to achieve both large number computation and high resolution. Finally, a 6-bit addition and multiplication computation cell is designed and implemented in 130nm CMOS process. It achieves 313ps of time resolution with varying multiplier and 1.926ps with varying multiplicand. The static power consumption of the chip is 11.09uW and the area is 0.0324mm2.