{"title":"采用铜聚酰亚胺薄膜多层基板的高速多芯片模块封装技术[用于B-ISDN]","authors":"S. Yamaguchi, Y. Ohno, H. Tomimuro","doi":"10.1109/IEMT.1993.398174","DOIUrl":null,"url":null,"abstract":"The authors describe a multichip module (MCM) having a copper-polyimide thin-film multilayer substrate that overcomes the problems of increased transmission loss at high frequencies maintaining crosstalk noise low, and the increased simultaneous switching noise with a larger number of LSI chips. The conductors are designed to be 10-/spl mu/m thick and 25-/spl mu/m wide to enable the transmission of high speed pulses at several Gb/s without decreasing the interconnection density while maintaining crosstalk noise as low as -30 dB. The dielectric thickness between the power and ground layers making up the current loop in the ceramic substrate is designed to be 50/spl mu/m, which gives rise to a low effective inductance.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Packaging technology for high-speed multichip module using copper-polyimide thin film multilayer substrate [for B-ISDN]\",\"authors\":\"S. Yamaguchi, Y. Ohno, H. Tomimuro\",\"doi\":\"10.1109/IEMT.1993.398174\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe a multichip module (MCM) having a copper-polyimide thin-film multilayer substrate that overcomes the problems of increased transmission loss at high frequencies maintaining crosstalk noise low, and the increased simultaneous switching noise with a larger number of LSI chips. The conductors are designed to be 10-/spl mu/m thick and 25-/spl mu/m wide to enable the transmission of high speed pulses at several Gb/s without decreasing the interconnection density while maintaining crosstalk noise as low as -30 dB. The dielectric thickness between the power and ground layers making up the current loop in the ceramic substrate is designed to be 50/spl mu/m, which gives rise to a low effective inductance.<<ETX>>\",\"PeriodicalId\":206206,\"journal\":{\"name\":\"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1993.398174\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1993.398174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
作者描述了一种多芯片模块(MCM),它具有铜聚酰亚胺薄膜多层衬底,克服了高频传输损耗增加的问题,保持了较低的串扰噪声,以及大量LSI芯片同时增加的开关噪声。导线设计为10-/spl mu/m厚,25-/spl mu/m宽,可以在不降低互连密度的情况下传输数Gb/s的高速脉冲,同时保持串扰噪声低至-30 dB。在陶瓷基板中,构成电流回路的功率层和接地层之间的介电厚度被设计为50/spl μ m /m,这导致有效电感较低。
Packaging technology for high-speed multichip module using copper-polyimide thin film multilayer substrate [for B-ISDN]
The authors describe a multichip module (MCM) having a copper-polyimide thin-film multilayer substrate that overcomes the problems of increased transmission loss at high frequencies maintaining crosstalk noise low, and the increased simultaneous switching noise with a larger number of LSI chips. The conductors are designed to be 10-/spl mu/m thick and 25-/spl mu/m wide to enable the transmission of high speed pulses at several Gb/s without decreasing the interconnection density while maintaining crosstalk noise as low as -30 dB. The dielectric thickness between the power and ground layers making up the current loop in the ceramic substrate is designed to be 50/spl mu/m, which gives rise to a low effective inductance.<>