Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398177
J. Kenney, W. Hunt, G. May
A yield model for gallium arsenide acoustic charge transport transversal filters is presented. It differs from previous IC yield models in that it is not assumed that individual failures of the nondestructive sensing taps necessarily cause a device failure. In this way, a redundancy in the number of taps included in the design is accounted for. Poisson statistics are used to describe the tap failures. A representative design example is presented, and the critical area for device failure is calculated. Yield is predicted for a range of defect densities, distribution functions, and redundancies. To verify the model, a Monte Carlo simulation is performed on an equivalent circuit model of the device. The results of the yield model are then compared to the Monte Carlo simulation. Better than 95% agreement is obtained for the Poisson model weighted by a triangular distribution function with one redundant circuit.<>
{"title":"Yield prediction of acoustic charge transport transversal filters","authors":"J. Kenney, W. Hunt, G. May","doi":"10.1109/IEMT.1993.398177","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398177","url":null,"abstract":"A yield model for gallium arsenide acoustic charge transport transversal filters is presented. It differs from previous IC yield models in that it is not assumed that individual failures of the nondestructive sensing taps necessarily cause a device failure. In this way, a redundancy in the number of taps included in the design is accounted for. Poisson statistics are used to describe the tap failures. A representative design example is presented, and the critical area for device failure is calculated. Yield is predicted for a range of defect densities, distribution functions, and redundancies. To verify the model, a Monte Carlo simulation is performed on an equivalent circuit model of the device. The results of the yield model are then compared to the Monte Carlo simulation. Better than 95% agreement is obtained for the Poisson model weighted by a triangular distribution function with one redundant circuit.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128382721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398222
J. Liu, A. Tillstrom
Results from a series of experimental studies on the effect of assembly process conditions and design rules on solder joint quality for 0,5 and 0,65 mm pitch surface mounted devices are summarized. A four-layer 200 /spl times/ 300 mm/sup 2/ test board is used for experimental purposes. The main objective of the work is to optimize design and manufacturing conditions for 0.5 mm pitch quad flatpack (QFP) components. A large number of design and process parameters are studied using factorial analysis. The parameters studied are pad width, lead inplanarity and lead sweep of component, placement position, squeegee speed and squeegee angle, number of strokes and surrounding temperature. It is found that at optimum design and process conditions, zero defect failure rate can be obtained for the 0.65 mm pitch components, while for the 0.5 mm pitch component, 400 ppm in solder joint failure rate can be obtained.<>
{"title":"Development of 0.5 and 0.65 mm pitch QFP technology in surface mounting","authors":"J. Liu, A. Tillstrom","doi":"10.1109/IEMT.1993.398222","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398222","url":null,"abstract":"Results from a series of experimental studies on the effect of assembly process conditions and design rules on solder joint quality for 0,5 and 0,65 mm pitch surface mounted devices are summarized. A four-layer 200 /spl times/ 300 mm/sup 2/ test board is used for experimental purposes. The main objective of the work is to optimize design and manufacturing conditions for 0.5 mm pitch quad flatpack (QFP) components. A large number of design and process parameters are studied using factorial analysis. The parameters studied are pad width, lead inplanarity and lead sweep of component, placement position, squeegee speed and squeegee angle, number of strokes and surrounding temperature. It is found that at optimum design and process conditions, zero defect failure rate can be obtained for the 0.65 mm pitch components, while for the 0.5 mm pitch component, 400 ppm in solder joint failure rate can be obtained.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398229
F. Chao
The impedance distribution measured by time domain reflectometry is utilized in estimating the thickness variation of the dielectric layer in a thin-film microstrip line. The relationship between dielectric thickness and impedance variation is derived based on an approximate formula. Measurements are carried out and a maximum linear fitting algorithm is proposed to correct the series resistance effect in the time domain reflectometer (TDR) data.<>
{"title":"Evaluate the dielectric thickness variation of thin-film microstrip line by time domain reflectometry","authors":"F. Chao","doi":"10.1109/IEMT.1993.398229","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398229","url":null,"abstract":"The impedance distribution measured by time domain reflectometry is utilized in estimating the thickness variation of the dielectric layer in a thin-film microstrip line. The relationship between dielectric thickness and impedance variation is derived based on an approximate formula. Measurements are carried out and a maximum linear fitting algorithm is proposed to correct the series resistance effect in the time domain reflectometer (TDR) data.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130483326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398170
J. Mitchell
Intelligent manufacturing systems (IMS) is an initiative to determine the feasibility of international collaborative R&D in advanced manufacturing and its industrial deployment. The two year feasibility study consists of: (1) a study of four critical issues for collaboration (methods of cooperation, intellectual property rights, funding and technical project areas) and (2) R&D test cases to provide experience and information for designing a full ongoing IMS program. Once the feasibility study is completed in January 1994, the international participants will decide whether to recommend a full IMS program, and if so, the form such a program should take.<>
{"title":"The intelligent manufacturing systems initiative","authors":"J. Mitchell","doi":"10.1109/IEMT.1993.398170","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398170","url":null,"abstract":"Intelligent manufacturing systems (IMS) is an initiative to determine the feasibility of international collaborative R&D in advanced manufacturing and its industrial deployment. The two year feasibility study consists of: (1) a study of four critical issues for collaboration (methods of cooperation, intellectual property rights, funding and technical project areas) and (2) R&D test cases to provide experience and information for designing a full ongoing IMS program. Once the feasibility study is completed in January 1994, the international participants will decide whether to recommend a full IMS program, and if so, the form such a program should take.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123418803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398178
R. Lee, W. A. Moreno, A. Radomski, N. Saini, D. Whittaker
High density interconnect technologies for advanced electronic systems are discussed. Primary focus is in the area of laser-created interconnects for quick turnaround prototyping of electronic circuits fabricated using standard very large scale integration (VLSI) process techniques. The laser restructuring of a specific application circuitry at the wafer or packaged chip level is accomplished by creating low electrical resistance links between conductors and cutting conductor lines using an integrated computer-controlled laser system. The restructuring of generic electronic circuits is an excellent technique for alternative low cost, quick turnaround with complete circuit similarity between the laser restructured prototype and the customized product for mass production.<>
{"title":"High density interconnects for rapid prototyping of electronic systems","authors":"R. Lee, W. A. Moreno, A. Radomski, N. Saini, D. Whittaker","doi":"10.1109/IEMT.1993.398178","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398178","url":null,"abstract":"High density interconnect technologies for advanced electronic systems are discussed. Primary focus is in the area of laser-created interconnects for quick turnaround prototyping of electronic circuits fabricated using standard very large scale integration (VLSI) process techniques. The laser restructuring of a specific application circuitry at the wafer or packaged chip level is accomplished by creating low electrical resistance links between conductors and cutting conductor lines using an integrated computer-controlled laser system. The restructuring of generic electronic circuits is an excellent technique for alternative low cost, quick turnaround with complete circuit similarity between the laser restructured prototype and the customized product for mass production.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125779748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398203
M. Yoshizawa, T. Sakurai
The delivery management method with marker lot and lot-sampling scheduling (LSS) has been developed. This method can reduce allocated memory compared to the conventional dynamic scheduling method. The reduction in allocated memory enables increasing the maximum number of lots to simulate the delivery date and to control turn-around-time (TAT). The accuracy of the simulated delivery date is within two days even for low-priority lots. Progress in processing is controlled by varying the resource allocation ratio for scheduling lots. This method is effective for delivery data control in manufacturing lines, including lots with various priority.<>
{"title":"An LSI delivery management method using lot-sampling scheduling","authors":"M. Yoshizawa, T. Sakurai","doi":"10.1109/IEMT.1993.398203","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398203","url":null,"abstract":"The delivery management method with marker lot and lot-sampling scheduling (LSS) has been developed. This method can reduce allocated memory compared to the conventional dynamic scheduling method. The reduction in allocated memory enables increasing the maximum number of lots to simulate the delivery date and to control turn-around-time (TAT). The accuracy of the simulated delivery date is within two days even for low-priority lots. Progress in processing is controlled by varying the resource allocation ratio for scheduling lots. This method is effective for delivery data control in manufacturing lines, including lots with various priority.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115864530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398214
M. Karnezos, R. Pendse, B. Afshari, F. Matta, K. Scholz
Demountable tape automated bonding (DTAB) is a VLSI package, developed and qualified for high performance (/spl Gt/100 MHz), high pincount (>400) ASICS with high power dissipation (/spl sim/40 W). Extensive reliability testing has been used to optimize the design as well as to qualify the package for product applications. The formal tests have been extended beyond the industry standards to include system level tests, designed to stress the pressure contact under conditions not expected from other equivalent packages. Testing reveals that this package produces very high reliability "sealed" contacts, although thin gold of 5-/spl mu/-in thickness is used instead of the thick 50-/spl mu/-in thickness conventionally required by other applications. The test and testing methodology are discussed, the results and the failure modes and analysis are presented. The design changes and materials used to eliminate the failures are described.<>
{"title":"Reliability of area array pressure contacts on the DTAB package","authors":"M. Karnezos, R. Pendse, B. Afshari, F. Matta, K. Scholz","doi":"10.1109/IEMT.1993.398214","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398214","url":null,"abstract":"Demountable tape automated bonding (DTAB) is a VLSI package, developed and qualified for high performance (/spl Gt/100 MHz), high pincount (>400) ASICS with high power dissipation (/spl sim/40 W). Extensive reliability testing has been used to optimize the design as well as to qualify the package for product applications. The formal tests have been extended beyond the industry standards to include system level tests, designed to stress the pressure contact under conditions not expected from other equivalent packages. Testing reveals that this package produces very high reliability \"sealed\" contacts, although thin gold of 5-/spl mu/-in thickness is used instead of the thick 50-/spl mu/-in thickness conventionally required by other applications. The test and testing methodology are discussed, the results and the failure modes and analysis are presented. The design changes and materials used to eliminate the failures are described.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124395607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398163
M. Nachnani, L. Nguyen, J. Bayan, H. Takiar
The concept of multichip module on laminated substrates (MCM-L) is being used in addressing high speed problems at a cost effective manner. One of the major problems associated with high speeds is the delta-I noise or the Ldi/dt noise due to the simultaneous switching of multiple outputs in digital circuits. An MCM-L layout approach that helps in reducing the signal delays, as well as decreasing the Ldi/dt noise by reducing the effective ground inductance without the use of a separate ground plane is described. Modeling and analytical techniques are used to characterize the ground path inductance in a single chip package, and to define the width of the ground trade in the MCM-L for optimal ground path inductance.<>
{"title":"A low-cost multichip (MCM-L) packaging solution","authors":"M. Nachnani, L. Nguyen, J. Bayan, H. Takiar","doi":"10.1109/IEMT.1993.398163","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398163","url":null,"abstract":"The concept of multichip module on laminated substrates (MCM-L) is being used in addressing high speed problems at a cost effective manner. One of the major problems associated with high speeds is the delta-I noise or the Ldi/dt noise due to the simultaneous switching of multiple outputs in digital circuits. An MCM-L layout approach that helps in reducing the signal delays, as well as decreasing the Ldi/dt noise by reducing the effective ground inductance without the use of a separate ground plane is described. Modeling and analytical techniques are used to characterize the ground path inductance in a single chip package, and to define the width of the ground trade in the MCM-L for optimal ground path inductance.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123601940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398188
A. Shuen
A general framework and empirical methodology for quantifying and characterizing co-developed knowhow assets built up in a technology partnership is developed. This framework and related hypotheses are tested on a US-Japanese co-development partnership project in the semiconductor industry. The resulting data and analysis demonstrate the usefulness of this approach for informing strategic and managerial decisions in areas ranging from technology sourcing, inter-firm transaction and governance costs and structuring multi-national co-development processes. The findings expand understanding of the project-level mechanisms underlying partnership learning and development processes, new process innovation and dynamic capabilities.<>
{"title":"Co-developed knowhow assets in technology partnerships","authors":"A. Shuen","doi":"10.1109/IEMT.1993.398188","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398188","url":null,"abstract":"A general framework and empirical methodology for quantifying and characterizing co-developed knowhow assets built up in a technology partnership is developed. This framework and related hypotheses are tested on a US-Japanese co-development partnership project in the semiconductor industry. The resulting data and analysis demonstrate the usefulness of this approach for informing strategic and managerial decisions in areas ranging from technology sourcing, inter-firm transaction and governance costs and structuring multi-national co-development processes. The findings expand understanding of the project-level mechanisms underlying partnership learning and development processes, new process innovation and dynamic capabilities.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123698392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398224
W.K. Shu
Response surface methodology is used to characterize a state-of-the-art wire bonder with a bottleneck capillary for fine pitch bonding. Regression analysis generates mathematical models to plot 3-D charts and contour charts of ball size and ball shear force as a function of wire bond parameters. A procedure is described to use contour charts to optimize bonding parameters. Bonding windows are identified by using bonding specification requirements and material/process constraints as boundary conditions.<>
{"title":"Fine pitch gold ball bonding optimization","authors":"W.K. Shu","doi":"10.1109/IEMT.1993.398224","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398224","url":null,"abstract":"Response surface methodology is used to characterize a state-of-the-art wire bonder with a bottleneck capillary for fine pitch bonding. Regression analysis generates mathematical models to plot 3-D charts and contour charts of ball size and ball shear force as a function of wire bond parameters. A procedure is described to use contour charts to optimize bonding parameters. Bonding windows are identified by using bonding specification requirements and material/process constraints as boundary conditions.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"1 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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