A. Dragan, Andrei Enache, A. Negut, A. Tache, G. Brezeanu
{"title":"一种高性能混合电压数字输出缓冲器","authors":"A. Dragan, Andrei Enache, A. Negut, A. Tache, G. Brezeanu","doi":"10.1109/SMICND.2018.8539840","DOIUrl":null,"url":null,"abstract":"A digital push-pull output buffer is designed and implemented in a 0.18μm CMOS EEPROM process. The buffer acts as an interface between an internal low voltage and an external, higher level voltage. The circuit can operate in a wide range of power supply voltages, from 1.6V to 5.6V, at data rates of up to 20 Mbps. These performances were achieved through topology changes to a classic digital buffer.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A High Performance Mixed-Voltage Digital Output Buffer\",\"authors\":\"A. Dragan, Andrei Enache, A. Negut, A. Tache, G. Brezeanu\",\"doi\":\"10.1109/SMICND.2018.8539840\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digital push-pull output buffer is designed and implemented in a 0.18μm CMOS EEPROM process. The buffer acts as an interface between an internal low voltage and an external, higher level voltage. The circuit can operate in a wide range of power supply voltages, from 1.6V to 5.6V, at data rates of up to 20 Mbps. These performances were achieved through topology changes to a classic digital buffer.\",\"PeriodicalId\":247062,\"journal\":{\"name\":\"2018 International Semiconductor Conference (CAS)\",\"volume\":\"178 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International Semiconductor Conference (CAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.2018.8539840\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Semiconductor Conference (CAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.2018.8539840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A High Performance Mixed-Voltage Digital Output Buffer
A digital push-pull output buffer is designed and implemented in a 0.18μm CMOS EEPROM process. The buffer acts as an interface between an internal low voltage and an external, higher level voltage. The circuit can operate in a wide range of power supply voltages, from 1.6V to 5.6V, at data rates of up to 20 Mbps. These performances were achieved through topology changes to a classic digital buffer.