{"title":"一种新的超低功耗射频集成电路功率优化技术","authors":"A. Shameli, P. Heydari","doi":"10.1145/1165573.1165639","DOIUrl":null,"url":null,"abstract":"This paper presents a novel power optimization technique for ultra-low power (ULP) RFICs. A new figure of merit, namely the g<sub>m </sub>f<sub>T</sub>- to-current ratio (g<sub>m</sub>f<sub>T</sub>/I<sub>D</sub>), is defined for a MOS transistor, which accounts for both the unity-gain frequency and current consumption. It is demonstrated both analytically and experimentally that the g<sub>m</sub>f<sub>T</sub>/I<sub>D</sub> reaches its maximum value in moderate inversion region. Next, using the proposed method, a power optimized common-gate low-noise amplifier (LNA) with active load has been designed and fabricated in a CMOS 0.18mum process operating at 950MHz. Measurement results show a noise-figure (NF) of 4.9dB and a small signal gain of 15.6dB with a record-breaking power dissipation of only 100muW","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"48","resultStr":"{\"title\":\"A Novel Power Optimization Technique for Ultra-Low Power RFICs\",\"authors\":\"A. Shameli, P. Heydari\",\"doi\":\"10.1145/1165573.1165639\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel power optimization technique for ultra-low power (ULP) RFICs. A new figure of merit, namely the g<sub>m </sub>f<sub>T</sub>- to-current ratio (g<sub>m</sub>f<sub>T</sub>/I<sub>D</sub>), is defined for a MOS transistor, which accounts for both the unity-gain frequency and current consumption. It is demonstrated both analytically and experimentally that the g<sub>m</sub>f<sub>T</sub>/I<sub>D</sub> reaches its maximum value in moderate inversion region. Next, using the proposed method, a power optimized common-gate low-noise amplifier (LNA) with active load has been designed and fabricated in a CMOS 0.18mum process operating at 950MHz. Measurement results show a noise-figure (NF) of 4.9dB and a small signal gain of 15.6dB with a record-breaking power dissipation of only 100muW\",\"PeriodicalId\":119229,\"journal\":{\"name\":\"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"48\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1165573.1165639\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1165573.1165639","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel Power Optimization Technique for Ultra-Low Power RFICs
This paper presents a novel power optimization technique for ultra-low power (ULP) RFICs. A new figure of merit, namely the gm fT- to-current ratio (gmfT/ID), is defined for a MOS transistor, which accounts for both the unity-gain frequency and current consumption. It is demonstrated both analytically and experimentally that the gmfT/ID reaches its maximum value in moderate inversion region. Next, using the proposed method, a power optimized common-gate low-noise amplifier (LNA) with active load has been designed and fabricated in a CMOS 0.18mum process operating at 950MHz. Measurement results show a noise-figure (NF) of 4.9dB and a small signal gain of 15.6dB with a record-breaking power dissipation of only 100muW
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