Enabling the synthesis of very long operation properties

In previous work, the high-level synthesis of operation properties has been proposed. In this work, we improve the existing algorithms in order to allow the synthesis of more efficient hardware models. Especially for very long properties no model could be generated before, because both the runtime of the synthesis process and the amount of used hardware resources were prohibitively high. The proposed improvements are threefold. First, the generated non-deterministic control automaton is replaced by a deterministic automaton using an optimized power set construction algorithm. This significantly reduces the number of registers in the generated model. Second, a property can contain local variables (freeze variables), that capture a value at a specific time step and provide this value throughout a property's life span. The scheduling of storage registers for these variables has been optimized. The last improvement merges equivalent assignments to output or state variables (commitments). The merging avoids not only the generation of redundant hardware resources but also simplifies the output multiplexer of the model. Finally, a case study is presented that involves an industrial design of a framer component. The design properties describe the processing of a complete data frame of 19440 cycles length. High-level synthesis and subsequent logic synthesis have been successful and show that the design methodology and synthesis algorithms result in a design with resource usage similar to the industrial component.