Real-time sub-pixel binocular ranging based on FPGA

Binocular stereo vision is an essential subject of computer vision research with numerous implications in 3D reconstruction. Binocular stereo vision algorithms, however, are computationally demanding and require a high processing units capability, Some conventional systems cannot meet the requirements of real-time and precision. To solve these issues, we employ a software-hardware co-design approach based on FPGA (Field Programmable Gate Arrays). According to the peculiarities of binocular stereo vision, We separate the system tasks into software and hardware portions that can fully utilize FPGA hardware acceleration and ARM (Advanced RISC Machine) data management. The parallel processing capabilities of FPGAs enable a comprehensive pipeline design synchronized with the same system clock to synchronously run multiple image processing components, considerably enhancing processing performance. This paper propose an improved image processing system that realizes binocular ranging through center point matching, We evaluated the design on the AXU3EG development board. The experimental results show that the system has high real-time performance. The system features a faster image processing rate and less expensive hardware than the conventional stereo matching ranging approach, and the ranging precision may be down to the sub-pixel level.