{"title":"CMOS电流模式全加法器的性能","authors":"K. Navi, A. Kazeminejad, D. Etiemble","doi":"10.1109/ISMVL.1994.302223","DOIUrl":null,"url":null,"abstract":"We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a standard 1.2 /spl mu/m CMOS technology. The performance of a binary voltage mode 1-bit adder is also presented. The binary version uses twice more transistors comparing with multivalued ones, but it is two or three times faster. Multivalued versions are more complicated to design and optimize. These results confirm the chip density advantage of multivalued circuits and the speed advantage of binary versions when using CMOS technologies.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":"{\"title\":\"Performance of CMOS current mode full adders\",\"authors\":\"K. Navi, A. Kazeminejad, D. Etiemble\",\"doi\":\"10.1109/ISMVL.1994.302223\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a standard 1.2 /spl mu/m CMOS technology. The performance of a binary voltage mode 1-bit adder is also presented. The binary version uses twice more transistors comparing with multivalued ones, but it is two or three times faster. Multivalued versions are more complicated to design and optimize. These results confirm the chip density advantage of multivalued circuits and the speed advantage of binary versions when using CMOS technologies.<<ETX>>\",\"PeriodicalId\":137138,\"journal\":{\"name\":\"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"30\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1994.302223\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1994.302223","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 30
摘要
介绍了三种不同的多值电流模式1位加法器的性能。这些电路采用标准的1.2 /spl μ m CMOS技术的电学参数进行了仿真。文中还介绍了一种二进制电压模式1位加法器的性能。二进制版本使用的晶体管比多值版本多一倍，但速度是多值版本的两到三倍。多值版本的设计和优化更为复杂。这些结果证实了在使用CMOS技术时，多值电路的芯片密度优势和二进制版本的速度优势。
We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a standard 1.2 /spl mu/m CMOS technology. The performance of a binary voltage mode 1-bit adder is also presented. The binary version uses twice more transistors comparing with multivalued ones, but it is two or three times faster. Multivalued versions are more complicated to design and optimize. These results confirm the chip density advantage of multivalued circuits and the speed advantage of binary versions when using CMOS technologies.<>
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