用于物联网应用的180nm低成本运算放大器

2021 IEEE Fifth Ecuador Technical Chapters Meeting (ETCM) Pub Date : 2021-10-12 DOI:10.1109/ETCM53643.2021.9590655

Kevin Vicuña, Cristhopher Mosquera, Mateo Rendón, Ariana Musello, M. Lanuzza, L. Prócel, R. Taco, L. Trojman

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引用次数: 1

摘要

本文介绍了一种带米勒补偿的两级运算放大器(opamp)的设计和布局后仿真，利用第三级作为输出缓冲器来驱动大负载。采用TSMC 0.18μm PDK在Cadence Virtuoso中进行设计、仿真和实现。该opamp采用1v轨对轨供电，功耗为20μW。后置布局仿真显示，单位增益带宽(UGBW)为69.18 MHz $(A_{v}=\mathbf{49.63dB})$，相位裕度(PM)大于86°，摆率为$19.87\mu\ mathm {v} _\ mathm {s}$;使我们的设计适用于小型和大型信号应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 180 nm Low-Cost Operational Amplifier for IoT Applications

This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamp) with Miller compensation, using a third stage that acts as output buffer to drive large loads. The TSMC 0.18μm PDK was used for the design, simulation and implementation in Cadence Virtuoso. The opamp exhibits 20μW power consumption with a 1-V rail-to-rail supply. Post layout simulation shows a unity gain bandwidth (UGBW) of 69.18 MHz $(A_{v}=\mathbf{49.63dB})$ with a phase margin (PM) larger than 86° and a Slew rate of $19.87\mu\mathrm{V}_\mathrm{s}$; making our design suitable for small and large signal applications.

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2021 IEEE Fifth Ecuador Technical Chapters Meeting (ETCM)

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