{"title":"工作函数工程可变垂直掺杂超结垂直单扩散MOS的设计与性能投影","authors":"Payal Nautiyal, Onika Parmar, Alok Naugarhiya, Shrish Verma","doi":"10.1109/CONECCT.2018.8482361","DOIUrl":null,"url":null,"abstract":"Workfunction engineering approach is utilized to design structure of variable vertical doped superjunction vertical single diffused MOS. To induce hole and electron plasma instead of n+ region, we have employed platinum and hafnium electrode respectively. Inclusion of these metals as contact, leads to the elimination of aluminum metal. Computational analysis reveal that proposed structure offer improvement in performance parameters such as specific ON-resistance and gate charge. Simulation results depict 6.82 % reduction in Ron. A and approximately 50 nC of gate charge reduction with negligible fall in breakdown voltage.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design and performance projection of workfunction engineered variable vertical doped superjunction vertical single diffused MOS\",\"authors\":\"Payal Nautiyal, Onika Parmar, Alok Naugarhiya, Shrish Verma\",\"doi\":\"10.1109/CONECCT.2018.8482361\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Workfunction engineering approach is utilized to design structure of variable vertical doped superjunction vertical single diffused MOS. To induce hole and electron plasma instead of n+ region, we have employed platinum and hafnium electrode respectively. Inclusion of these metals as contact, leads to the elimination of aluminum metal. Computational analysis reveal that proposed structure offer improvement in performance parameters such as specific ON-resistance and gate charge. Simulation results depict 6.82 % reduction in Ron. A and approximately 50 nC of gate charge reduction with negligible fall in breakdown voltage.\",\"PeriodicalId\":430389,\"journal\":{\"name\":\"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CONECCT.2018.8482361\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONECCT.2018.8482361","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and performance projection of workfunction engineered variable vertical doped superjunction vertical single diffused MOS
Workfunction engineering approach is utilized to design structure of variable vertical doped superjunction vertical single diffused MOS. To induce hole and electron plasma instead of n+ region, we have employed platinum and hafnium electrode respectively. Inclusion of these metals as contact, leads to the elimination of aluminum metal. Computational analysis reveal that proposed structure offer improvement in performance parameters such as specific ON-resistance and gate charge. Simulation results depict 6.82 % reduction in Ron. A and approximately 50 nC of gate charge reduction with negligible fall in breakdown voltage.