An Efficient of High-Speed and High precision Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation

Finite field arithmetic is becoming increasingly a very prominent solution for calculations in many applications. In this paper, complexity and delay of six different multipliers (Mastrovito multiplier, Paar-Roelse multiplier, Massey- Omura multiplier, Hasan-Masoleh multiplier, Berlekamp multiplier and Karatsuba multiplier) are compared. Also this paper presents a modified multiplier based on Karatsuba multiplication algorithm. To optimize the Karatsuba multiplication algorithm, the product terms are splited into two alternative forms and all the terms are expressed in the repeated fashion. This Modified architecture saves the 14.9% computation time and it consumes 45.5% less slices than existing Karatsuba multiplier. The proposed architecture has been simulated and synthesized by Xilinx ISE design suite for Spartan & Vertex device family. The new architecture is Simple & easy. The proposed Modified Karatsuba Multiplier (MKM) is also applied to compute the circular convolution for DSP application. In Spartan3E FPGA device family, computation of 8-bit circular convolution using Modified Karatsuba Algorithm (MKA) is 26.5% faster than Karatsuba Algorithm (KA). It also consumes 61.7% less slices than existing KA based Convolution.