Hardware acceleration of novel chaos-based image encryption for IoT applications

In this paper, we propose a new chaos-based image encryption algorithm that combines Arnold's Cat and cascaded discrete Duffing equations maps for the confusion and diffusion stages of an image cryptosystem. The algorithm performs only one Arnold's Cat shuffle on the encryption side using two different keys instead of several shuffles used in conventional implementations. The security analysis of the proposed algorithm proves robustness when compared to state-of-the-art chaos-based encryption algorithms with less runtime and simpler operations. A complete accelerated hardware design of the proposed algorithm is implemented on Xilinx Zynq XC7Z020 FPGA board. For a 512 × 512 image, the hardware design achieves a maximum frequency of 135 MHz encrypting 256 fps which meets the real-time requirements of IoT applications.