{"title":"利用缓存内存结构中的容错性","authors":"Somak R. Das, Sowvik Dey","doi":"10.1109/ICHPCA.2014.7045291","DOIUrl":null,"url":null,"abstract":"Cache memories can work as buffer between processors and main memories. It enables rapid access of data for a processor in operation. Set-associativity provides optimality in mapping of cache memories and reduction of cache miss probability. Design of a high speed cache has always been a desirable criteria of hardware experts as it increases processor utilization. Exploiting fault tolerance within such a cache memory of higher throughput ensures reliable data transfer and is an open research problem in the domain of high-performance computing. This paper proposes a design of low-order interleaved set-associative cache memory with lesser response time and exploits a high degree of fault tolerance.","PeriodicalId":197528,"journal":{"name":"2014 International Conference on High Performance Computing and Applications (ICHPCA)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Exploiting fault tolerance within cache memory structures\",\"authors\":\"Somak R. Das, Sowvik Dey\",\"doi\":\"10.1109/ICHPCA.2014.7045291\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cache memories can work as buffer between processors and main memories. It enables rapid access of data for a processor in operation. Set-associativity provides optimality in mapping of cache memories and reduction of cache miss probability. Design of a high speed cache has always been a desirable criteria of hardware experts as it increases processor utilization. Exploiting fault tolerance within such a cache memory of higher throughput ensures reliable data transfer and is an open research problem in the domain of high-performance computing. This paper proposes a design of low-order interleaved set-associative cache memory with lesser response time and exploits a high degree of fault tolerance.\",\"PeriodicalId\":197528,\"journal\":{\"name\":\"2014 International Conference on High Performance Computing and Applications (ICHPCA)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on High Performance Computing and Applications (ICHPCA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICHPCA.2014.7045291\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on High Performance Computing and Applications (ICHPCA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICHPCA.2014.7045291","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Exploiting fault tolerance within cache memory structures
Cache memories can work as buffer between processors and main memories. It enables rapid access of data for a processor in operation. Set-associativity provides optimality in mapping of cache memories and reduction of cache miss probability. Design of a high speed cache has always been a desirable criteria of hardware experts as it increases processor utilization. Exploiting fault tolerance within such a cache memory of higher throughput ensures reliable data transfer and is an open research problem in the domain of high-performance computing. This paper proposes a design of low-order interleaved set-associative cache memory with lesser response time and exploits a high degree of fault tolerance.