一种用于dpll的90纳米CMOS门环振荡器游标时间-数字转换器

2011 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2011-10-13 DOI:10.1109/ESSCIRC.2011.6045006

P. Lu, P. Andreani, A. Liscidini

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引用次数: 11

摘要

在改进的游标时间-数字转换器(TDC)中，两个门控环振荡器(GRO)作为延迟线。标准游标TDC本来就很小的量化噪声，通过GRO运算进一步一阶成形。TDC采用90nm CMOS技术实现，在800kHz的信号带宽下实现了优于5ps的分辨率。当工作在25MHz时，电流消耗从1.2V到3mA。

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A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs

Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.

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2011 Proceedings of the ESSCIRC (ESSCIRC)

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