分数阶锁相环频率合成器

M. Stork, P. Kašpar
{"title":"分数阶锁相环频率合成器","authors":"M. Stork, P. Kašpar","doi":"10.1109/SCS.2003.1226965","DOIUrl":null,"url":null,"abstract":"The fractional frequency synthesizer is similar to the divide-by-N phase-locked loop (PLL) (divider in feedback path). However, the output frequency of the voltage-controlled oscillator (VCO) is not restricted to integral multiples of the reference signal only. Rather, it can also be locked to the fractional multiples, with the result of a substantial reduction of the frequency tuning step in the useful bandwidth of the PLL without reduction of its pass band. Consequently, these frequency synthesizers have both high frequency resolution and short settling time, two essential requirements for modern applications, for example, in modern radio sets. The major difficulties are spurious signals generated in fractional divider system. In this paper, the new fractional PLL frequency synthesizer with Σ-Δ modulator is described. A complete fractional PLL was simulated, constructed and measured.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Fractional phase-locked loop frequency synthesizer\",\"authors\":\"M. Stork, P. Kašpar\",\"doi\":\"10.1109/SCS.2003.1226965\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The fractional frequency synthesizer is similar to the divide-by-N phase-locked loop (PLL) (divider in feedback path). However, the output frequency of the voltage-controlled oscillator (VCO) is not restricted to integral multiples of the reference signal only. Rather, it can also be locked to the fractional multiples, with the result of a substantial reduction of the frequency tuning step in the useful bandwidth of the PLL without reduction of its pass band. Consequently, these frequency synthesizers have both high frequency resolution and short settling time, two essential requirements for modern applications, for example, in modern radio sets. The major difficulties are spurious signals generated in fractional divider system. In this paper, the new fractional PLL frequency synthesizer with Σ-Δ modulator is described. A complete fractional PLL was simulated, constructed and measured.\",\"PeriodicalId\":375963,\"journal\":{\"name\":\"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-07-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SCS.2003.1226965\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCS.2003.1226965","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

分数频率合成器类似于分n锁相环(反馈路径中的分频器)。然而,压控振荡器(VCO)的输出频率并不局限于参考信号的整数倍。相反,它也可以被锁定到分数倍,其结果是在锁相环的有用带宽中大幅度减少了频率调谐步骤,而不减少其通频带。因此,这些频率合成器具有高频率分辨率和短的稳定时间,这是现代应用的两个基本要求,例如,在现代收音机中。分数分法器系统的主要难点是产生杂散信号。本文介绍了一种新型的Σ-Δ调制器分数阶锁相环频率合成器。模拟、构造和测量了一个完整的分数阶锁相环。
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Fractional phase-locked loop frequency synthesizer
The fractional frequency synthesizer is similar to the divide-by-N phase-locked loop (PLL) (divider in feedback path). However, the output frequency of the voltage-controlled oscillator (VCO) is not restricted to integral multiples of the reference signal only. Rather, it can also be locked to the fractional multiples, with the result of a substantial reduction of the frequency tuning step in the useful bandwidth of the PLL without reduction of its pass band. Consequently, these frequency synthesizers have both high frequency resolution and short settling time, two essential requirements for modern applications, for example, in modern radio sets. The major difficulties are spurious signals generated in fractional divider system. In this paper, the new fractional PLL frequency synthesizer with Σ-Δ modulator is described. A complete fractional PLL was simulated, constructed and measured.
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