High speed data bus design validation

The SAE Linear Implementation Task Group has developed the SAE Linear Token Passing Multiplex Data Bus Standard (AS4074.1). A validation plan which will define the test requirements for determining that an implementation of the standard meets the requirements of SAE AS4074.1 is discussed. Once completed, the test requirements contained in this plan will be executed on bus interface units (BIUs) for validation purposes. The author describes the use of a validation model that incorporates many of the capabilities of the validation test plan. This model can also be thought of as a VHDL (VHSIC Hardware Description Language) behavioral representation of the SAE Linear Token Passing Multiplex Data Bus Standard. It is tightly coupled to the standard and provides a model that can be used during the BIU development to validate the design.<>