Pub Date : 1991-08-01DOI: 10.1109/NAECON.1991.165788
R. E. Niggeman, S. Peecher, G. Rozman
Sundstrand is actively investigating the technologies required by 270-VDC, hybrid 115-VAC systems to meet power quality and stability requirements when supplying largely negative impedance loads. The design of the technology demonstrator system has focused on assembling a highly flexible test system that is capable of providing the data and experience necessary to successfully design and build a high-efficiency, high-reliability, fault-tolerant, low-weight, low-cost hybrid aircraft electrical system for future applications. Data taken to date indicate that voltage regulation requirements of Aerospace Standard AS1831 or MIL-STD-MS704E can be met with state-of-the-art technology. It is demonstrated that with improper source/load impedance matching, system instability can occur. Measurements of source and load impedance compare reasonably well in both magnitude and phase with analytical predictions.<>
{"title":"270-VDC/hybrid 115-VAC electric power generating system technology demonstrator","authors":"R. E. Niggeman, S. Peecher, G. Rozman","doi":"10.1109/NAECON.1991.165788","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165788","url":null,"abstract":"Sundstrand is actively investigating the technologies required by 270-VDC, hybrid 115-VAC systems to meet power quality and stability requirements when supplying largely negative impedance loads. The design of the technology demonstrator system has focused on assembling a highly flexible test system that is capable of providing the data and experience necessary to successfully design and build a high-efficiency, high-reliability, fault-tolerant, low-weight, low-cost hybrid aircraft electrical system for future applications. Data taken to date indicate that voltage regulation requirements of Aerospace Standard AS1831 or MIL-STD-MS704E can be met with state-of-the-art technology. It is demonstrated that with improper source/load impedance matching, system instability can occur. Measurements of source and load impedance compare reasonably well in both magnitude and phase with analytical predictions.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133882107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165740
D. Brown, R. Passow, S. Rasset, M. Russell, C. Hudson
IEEE 1076 compatible VHDL (VHSIC Hardware Description Language) was used to create a behavioral model for a complex ASIC (application-specific integrated circuit) design. Specifically, VHDL was used in the development of the HTIU2000 Test-bus Interface Unit. The design process incorporated VHDL from the beginning of the design cycle; the behavioral description of the HTIU2000 was performed in VHDL from the beginning of the process, not converted to VHDL from another hardware description language. The behavioral model was successfully converted to a gate-level implementation in a standard cell library using some synthesis of the VHDL code. The part was fabricated and the behavior of the parts matched that of the VHDL model. The successful fabrication of the HTIU2000 chips, illustrates that VHDL and design synthesis can be used to design complex ASICs.<>
{"title":"Design of a 25000 gate ASIC using VHDL","authors":"D. Brown, R. Passow, S. Rasset, M. Russell, C. Hudson","doi":"10.1109/NAECON.1991.165740","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165740","url":null,"abstract":"IEEE 1076 compatible VHDL (VHSIC Hardware Description Language) was used to create a behavioral model for a complex ASIC (application-specific integrated circuit) design. Specifically, VHDL was used in the development of the HTIU2000 Test-bus Interface Unit. The design process incorporated VHDL from the beginning of the design cycle; the behavioral description of the HTIU2000 was performed in VHDL from the beginning of the process, not converted to VHDL from another hardware description language. The behavioral model was successfully converted to a gate-level implementation in a standard cell library using some synthesis of the VHDL code. The part was fabricated and the behavior of the parts matched that of the VHDL model. The successful fabrication of the HTIU2000 chips, illustrates that VHDL and design synthesis can be used to design complex ASICs.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123052244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165916
D.L. Nichols, P.M. Vicen, R.B. Marcum
It is noted that the maturity of software technologies, as they relate to integrated diagnostics, lags greatly behind hardware integrated diagnostics technologies. The authors present a case for advancing these types of software technologies. Software integrated diagnostics (SID) is defined as the subset of integrated diagnostics that concerns itself with the detection and isolation of errors in the operation of embedded software. It is recognized that errors in the operation of software may be the result of a number of causes, including requirements and design deficiencies, coding errors, hardware failures, or transient system effects. Within this context, SID concerns itself with two areas, detecting problems that manifest themselves in the software and isolating the source of the problems. The need to combine software and hardware failure isolation elevates SID to a system level function. The authors discuss an approach to developing SID technologies.<>
{"title":"Software-missing piece in the integrated diagnostics puzzle","authors":"D.L. Nichols, P.M. Vicen, R.B. Marcum","doi":"10.1109/NAECON.1991.165916","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165916","url":null,"abstract":"It is noted that the maturity of software technologies, as they relate to integrated diagnostics, lags greatly behind hardware integrated diagnostics technologies. The authors present a case for advancing these types of software technologies. Software integrated diagnostics (SID) is defined as the subset of integrated diagnostics that concerns itself with the detection and isolation of errors in the operation of embedded software. It is recognized that errors in the operation of software may be the result of a number of causes, including requirements and design deficiencies, coding errors, hardware failures, or transient system effects. Within this context, SID concerns itself with two areas, detecting problems that manifest themselves in the software and isolating the source of the problems. The need to combine software and hardware failure isolation elevates SID to a system level function. The authors discuss an approach to developing SID technologies.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124875409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165754
G. Nelson, D. J. Bartnik, S. Lins
An ultra-low profile (ULP) fiber-optic transmitter has been developed to meet the demanding requirements of military avionic applications. The package meets the 0.120-in height requirement of military avionic standard electronic modules (SEMs). The optical design allows a removable connector and provides efficient fiber coupling over a wide temperature range. The electrical design provides temperature-compensated wide-bandwidth laser modulation from -55 to 125 degrees C. The electronics provide laser modulation up to 1.4 GHz and temperature compensation of optical power within 0.25 dB.<>
{"title":"Gigabit 0.120 inch tall, connectorized laser transmitter for military avionic applications","authors":"G. Nelson, D. J. Bartnik, S. Lins","doi":"10.1109/NAECON.1991.165754","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165754","url":null,"abstract":"An ultra-low profile (ULP) fiber-optic transmitter has been developed to meet the demanding requirements of military avionic applications. The package meets the 0.120-in height requirement of military avionic standard electronic modules (SEMs). The optical design allows a removable connector and provides efficient fiber coupling over a wide temperature range. The electrical design provides temperature-compensated wide-bandwidth laser modulation from -55 to 125 degrees C. The electronics provide laser modulation up to 1.4 GHz and temperature compensation of optical power within 0.25 dB.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125852733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165906
V. Dasigi, K. Thirunarayan
The authors explain some of the relationships of the Boolean minimization problem (BMP) to a formalization of abductive inference called parsimonious covering (PC). Abductive inference often occurs in diagnostic problems such as finding the causes of circuit faults or determining the disease causing the symptoms reported by a patient. Parsimonious covering involves covering all observed facts by means of a parsimonious set of explanations that can account for the observation. It is shown that only the prime implicants of a given Boolean function in a BMP, rather than any general product terms, are considered analogous to disorders in a PC problem.<>
{"title":"On the relationship between parsimonious covering and Boolean minimization","authors":"V. Dasigi, K. Thirunarayan","doi":"10.1109/NAECON.1991.165906","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165906","url":null,"abstract":"The authors explain some of the relationships of the Boolean minimization problem (BMP) to a formalization of abductive inference called parsimonious covering (PC). Abductive inference often occurs in diagnostic problems such as finding the causes of circuit faults or determining the disease causing the symptoms reported by a patient. Parsimonious covering involves covering all observed facts by means of a parsimonious set of explanations that can account for the observation. It is shown that only the prime implicants of a given Boolean function in a BMP, rather than any general product terms, are considered analogous to disorders in a PC problem.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126188077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165766
C.W. Rhodine
A 4-Mb DRAM (dynamic random access memory) family which improves upon the performance of the 1 Mb DRAM family is described. While increasing storage density and reducing memory access times, overall chip size is minimally affected. Development of 0.9- mu m CMOS technology for use on the 4-Mb DRAM allowed immediate speed and size improvements over the 1-Mb DRAM. Continual review of lessons learned on previous design insures that each successive DRAM generation is both more efficient in terms of architecture and more reliable in system use. In the case of the 4-Mb DRAM, this dedication to improvement has resulted tin a 20% speed enhancement, moderate size increase (1.6X), and improved reliability results.<>
描述了在1mb DRAM系列性能基础上改进的4mb DRAM(动态随机存取存储器)系列。在增加存储密度和减少内存访问时间的同时，总体芯片尺寸受到的影响最小。用于4mb DRAM的0.9 μ m CMOS技术的开发使速度和尺寸比1mb DRAM得到了即时改进。不断回顾以前设计的经验教训，确保每一代DRAM在架构方面更高效，在系统使用中更可靠。在4mb DRAM的情况下，这种致力于改进的努力导致了20%的速度提高，适度的尺寸增加(1.6倍)，并提高了可靠性。
{"title":"Texas Instruments' 4 Mb DRAM-a new, faster generation of DRAM","authors":"C.W. Rhodine","doi":"10.1109/NAECON.1991.165766","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165766","url":null,"abstract":"A 4-Mb DRAM (dynamic random access memory) family which improves upon the performance of the 1 Mb DRAM family is described. While increasing storage density and reducing memory access times, overall chip size is minimally affected. Development of 0.9- mu m CMOS technology for use on the 4-Mb DRAM allowed immediate speed and size improvements over the 1-Mb DRAM. Continual review of lessons learned on previous design insures that each successive DRAM generation is both more efficient in terms of architecture and more reliable in system use. In the case of the 4-Mb DRAM, this dedication to improvement has resulted tin a 20% speed enhancement, moderate size increase (1.6X), and improved reliability results.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126772453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165738
M. S. Russell, J. C. Hansen, L.J. Merboth
The Unisys/AT&T General Purpose Processing Element (GPPE) module is described. The GPPE, which is based upon next-generation reduced instruction set computer (RISC) microprocessor technology, combines the 32-b instruction set architecture (ISA) and 33-MHz operation. Using a commercial ISA and open architecture results in the most cost-effective, full-featured, militarized design available on a single-width SEM-E module. Other GPPE features include a multilayer data security mechanism and extensive features to protect classified data. The 6 Mbytes of SRAM and 512 kbytes of EEPROM available on the GPPE are consistent with large RISC addressing spaces and real-time operating system requirements. Support of the Joint Integrated Avionics Working Group two-level maintenance concepts is provided.<>
{"title":"A high performance general purpose processing element for avionic applications","authors":"M. S. Russell, J. C. Hansen, L.J. Merboth","doi":"10.1109/NAECON.1991.165738","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165738","url":null,"abstract":"The Unisys/AT&T General Purpose Processing Element (GPPE) module is described. The GPPE, which is based upon next-generation reduced instruction set computer (RISC) microprocessor technology, combines the 32-b instruction set architecture (ISA) and 33-MHz operation. Using a commercial ISA and open architecture results in the most cost-effective, full-featured, militarized design available on a single-width SEM-E module. Other GPPE features include a multilayer data security mechanism and extensive features to protect classified data. The 6 Mbytes of SRAM and 512 kbytes of EEPROM available on the GPPE are consistent with large RISC addressing spaces and real-time operating system requirements. Support of the Joint Integrated Avionics Working Group two-level maintenance concepts is provided.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116116500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165770
Zhiyong Gao, Zhenkang Shen, Yiping Jing
A two-stage correlation method which can realize fast registration of two digital images in the case of low SNR (signal-to-noise ratio) is proposed, and a new algorithm for roughly searching for a registration position-sequential measure test algorithm (SMTA) is given. Monte-Carlo simulation has shown that the method is over two orders of magnitude faster than the optimal MSD algorithm and far faster than the sequential SSDA, and that its performance is almost as good as the optimal MSD. It can perform well under the condition that the SNR is so low and the length of subimage data is so short that SSDA cannot be used to match at all. The fast correlation method virtually satisfies the demands of some navigation, tracking, and guidance systems for real-time matching.<>
{"title":"Two-stage correlation method in low SNR for fast image registration","authors":"Zhiyong Gao, Zhenkang Shen, Yiping Jing","doi":"10.1109/NAECON.1991.165770","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165770","url":null,"abstract":"A two-stage correlation method which can realize fast registration of two digital images in the case of low SNR (signal-to-noise ratio) is proposed, and a new algorithm for roughly searching for a registration position-sequential measure test algorithm (SMTA) is given. Monte-Carlo simulation has shown that the method is over two orders of magnitude faster than the optimal MSD algorithm and far faster than the sequential SSDA, and that its performance is almost as good as the optimal MSD. It can perform well under the condition that the SNR is so low and the length of subimage data is so short that SSDA cannot be used to match at all. The fast correlation method virtually satisfies the demands of some navigation, tracking, and guidance systems for real-time matching.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122495467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165814
J. E. Kester
The author surveys some of the lessons learned in conversion projects for FORTRAN and BASIC into Ada, and in interfacing FORTRAN into Ada. He discusses design issues to be explored and resolved before coding begins. In general, problems will be found not in the control constructs of the languages (loops, IF-THEN statements, error exception handling) but in the representation of data types, and, to a lesser extent, the mathematical operations performed on various types. Examples show what to look for during design to prevent pitfalls encountered during coding and testing. Some solutions may require debugger analysis, while others may be implemented with specific coding practice (hence making the Ada host-specific).<>
{"title":"Pain and triumph: lessons learned from converting or interfacing other languages into Ada","authors":"J. E. Kester","doi":"10.1109/NAECON.1991.165814","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165814","url":null,"abstract":"The author surveys some of the lessons learned in conversion projects for FORTRAN and BASIC into Ada, and in interfacing FORTRAN into Ada. He discusses design issues to be explored and resolved before coding begins. In general, problems will be found not in the control constructs of the languages (loops, IF-THEN statements, error exception handling) but in the representation of data types, and, to a lesser extent, the mathematical operations performed on various types. Examples show what to look for during design to prevent pitfalls encountered during coding and testing. Some solutions may require debugger analysis, while others may be implemented with specific coding practice (hence making the Ada host-specific).<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129192670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-05-20DOI: 10.1109/NAECON.1991.165848
D. Moitra, G. Montanaro, C. Chalek, H. Chang
The authors present novel interactive graphical techniques for performing US Air Force planning tasks such as deploying aircraft and weapons against desired targets, determining the availability of resources, performing a cost-benefit analysis to improve resource utilization, and coordinating interdependent missions. The most fundamental aspect of force-level planning is that it is an iterative process, during each cycle of which it is important to be able to visualize the interdependence among the decision variables, and to be able to gauge the impact of modifying specific decisions. Traditional text-based techniques deny the planner the power of the interactive graphical medium for visualizing these dependencies, and for gauging the impact of proposed changes. In contrast, the proposed techniques help the planner to understand arbitrary fragments of the current state of the mission plans, and incrementally improve them to achieve tactical objectives.<>
{"title":"New graphical techniques for strategic and tactical planning","authors":"D. Moitra, G. Montanaro, C. Chalek, H. Chang","doi":"10.1109/NAECON.1991.165848","DOIUrl":"https://doi.org/10.1109/NAECON.1991.165848","url":null,"abstract":"The authors present novel interactive graphical techniques for performing US Air Force planning tasks such as deploying aircraft and weapons against desired targets, determining the availability of resources, performing a cost-benefit analysis to improve resource utilization, and coordinating interdependent missions. The most fundamental aspect of force-level planning is that it is an iterative process, during each cycle of which it is important to be able to visualize the interdependence among the decision variables, and to be able to gauge the impact of modifying specific decisions. Traditional text-based techniques deny the planner the power of the interactive graphical medium for visualizing these dependencies, and for gauging the impact of proposed changes. In contrast, the proposed techniques help the planner to understand arbitrary fragments of the current state of the mission plans, and incrementally improve them to achieve tactical objectives.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116497294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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