Software Performance Study of a video decoder on SoC Zynq-7000

Nowadays, high video resolution such as Full HD, 4K and 8K will become the most used in video systems. These resolutions are integrated in the HEVC (High Efficiency Video Coding) norm. However, these performances have been accompanied by an algorithmic complexity which affects directly the processing time. To overcome this complexity, parallel architectures presents an interesting solution for this problem. As part of this goal, we propose a solution based on SoC (System On Chip) technology for the implementation of the HEVC intra decoding chain. The HM16.20 code was used for HEVC encoding and decoding, and the Xilinx Vivado tool for the implementation of this code on the Zynq-7000 platform. In this work, we present a performance profiling in terms of execution time, power consumption and the used hardware resources.