全单片1.25ghz cmos频率合成器

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586249

M. Soyuer, J. Ewen, H.L. Chuang

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引用次数: 18

摘要

设计了一种采用0.45pm CMOS技术实现的全单片频率合成器锁相环电路。测压夹在1.25 giz下从3.3V电源消耗27omw。生成的时钟的RMS抖动为1.4~s。除电源解耦电容外，不使用外部元件。

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A Fully Monolithic 1.25ghz cmos Frequency Synthesizer

A fully monolithic frcqucncy synthesizer PLL circuit implcmented in a 0.45pm CMOS tcchnology is prcscntcd. ?’lie test cliip consumcs 27omw at 1.25GIIz from a 3.3V supply. 1 he rms jitter of the gcnerated clock is 1.4~s. No external componcnts are uscd except supply dccoupling capacitois.

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Proceedings of 1994 IEEE Symposium on VLSI Circuits

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