{"title":"一种用于HDTV视频编码器的可变长度编码ASIC芯片","authors":"Jin-young Yang, Jinwoong Kim, Sang Gyu Park","doi":"10.1109/icce.1997.625958","DOIUrl":null,"url":null,"abstract":"This paper describes functions and architecture of a VLC ASIC chip specially designed for a parallel processing HDTV video encoder. It is designed to have several operating modes which is very flexible in that it can process in a master or slave sub-picture encoding module of an HDTV encoder, as well as in a standalone encoder for several video input formats according to MPEG-2 MP@ML. The VLC chip is fabricated using 0 . 8 ~ CMOS gate array technology, and runs at 27MHz clock rate.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Variable Length Coding ASIC Chip For HDTV Video Encoders\",\"authors\":\"Jin-young Yang, Jinwoong Kim, Sang Gyu Park\",\"doi\":\"10.1109/icce.1997.625958\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes functions and architecture of a VLC ASIC chip specially designed for a parallel processing HDTV video encoder. It is designed to have several operating modes which is very flexible in that it can process in a master or slave sub-picture encoding module of an HDTV encoder, as well as in a standalone encoder for several video input formats according to MPEG-2 MP@ML. The VLC chip is fabricated using 0 . 8 ~ CMOS gate array technology, and runs at 27MHz clock rate.\",\"PeriodicalId\":127085,\"journal\":{\"name\":\"1997 International Conference on Consumer Electronics\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icce.1997.625958\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icce.1997.625958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Variable Length Coding ASIC Chip For HDTV Video Encoders
This paper describes functions and architecture of a VLC ASIC chip specially designed for a parallel processing HDTV video encoder. It is designed to have several operating modes which is very flexible in that it can process in a master or slave sub-picture encoding module of an HDTV encoder, as well as in a standalone encoder for several video input formats according to MPEG-2 MP@ML. The VLC chip is fabricated using 0 . 8 ~ CMOS gate array technology, and runs at 27MHz clock rate.
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