改进的写入余量6T-SRAM用于低电源电压应用

2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI:10.1109/SOCCON.2009.5398053

F. Moradi, D. Wisland, H. Mahmoodi, T. Cao

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引用次数: 5

摘要

本文提出了一种提高6T-SRAM单元写入裕度的新技术。使用这种技术，亚阈值SRAM单元的面积减少，写周期也得到了显著改善，面积开销更低。在该技术中，使用PMOS堆叠网络来评估写周期。基于65nm器件的弱反转特性，提出了降低6T-SRAM在亚阈值区域的面积开销的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improved write margin 6T-SRAM for low supply voltage applications

In this paper a new technique to increase the write margin of 6T-SRAM cell is proposed. Using this technique the area of subthreshold SRAM cell is reduced and also the Write cycle is improved significantly with a lower area overhead. In this technique, PMOS stacked network is used to evaluate the write cycle. Based on behavior of devices in 65nm for weak inversion operation, this technique is proposed to decrease area overhead of 6T-SRAM in subthreshold region.

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2009 IEEE International SOC Conference (SOCC)

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