{"title":"当前RISC和CISC cpu的实用缓存设计技术","authors":"J. Handy","doi":"10.1109/ELECTR.1991.718222","DOIUrl":null,"url":null,"abstract":"Cache memories are moving into the forefront of popularity. Most microprocessor system designers can now expect to be called upon to design or implement a cache at some time in their carreers. It is somewhat difficult deciding where to start when first confronted with the task of designing a cache from scratch. This paper will focus on techniques which can be used in microprocessor cache designs to improve system throughput. Examples are shown using Intel's i486 processor, and the P3000 RISC processor.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Practical Cache Design Techniques For Today's RISC And CISC CPUS\",\"authors\":\"J. Handy\",\"doi\":\"10.1109/ELECTR.1991.718222\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cache memories are moving into the forefront of popularity. Most microprocessor system designers can now expect to be called upon to design or implement a cache at some time in their carreers. It is somewhat difficult deciding where to start when first confronted with the task of designing a cache from scratch. This paper will focus on techniques which can be used in microprocessor cache designs to improve system throughput. Examples are shown using Intel's i486 processor, and the P3000 RISC processor.\",\"PeriodicalId\":339281,\"journal\":{\"name\":\"Electro International, 1991\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-04-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electro International, 1991\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELECTR.1991.718222\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electro International, 1991","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECTR.1991.718222","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Practical Cache Design Techniques For Today's RISC And CISC CPUS
Cache memories are moving into the forefront of popularity. Most microprocessor system designers can now expect to be called upon to design or implement a cache at some time in their carreers. It is somewhat difficult deciding where to start when first confronted with the task of designing a cache from scratch. This paper will focus on techniques which can be used in microprocessor cache designs to improve system throughput. Examples are shown using Intel's i486 processor, and the P3000 RISC processor.
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