Analysis and Implementation of Hybrid FIR Architecture in Speech Processor

Hearing aid is an electronic gadget precisely used into the internal ear which reestablishes halfway hearing to smooth hearing. The discourse processor of CI parts the sound-related sign into groups of various frequencies and changes over them into appropriate codes for animating the cathodes in cochlea of ear. The cathode actuates sound-related nerve filaments to give hearing sensation. The expense of the CI alone goes to around 100,000 US dollars. For the efficient less well-to-do individuals with hearing sickness, it might be too exorbitant to even consider affording for this hardware to recoup from the conference misfortune. It gets important to cut down the expense. The cost decrease might be accomplished with diminished region, low force and rapid activity of the CI. This goal intuited both the simple and the computerized based CI originators to inquire about their techniques to give individuals less expensive and profoundly understandable CI. The primary objective of this paper is to develop reconfigurable DSP architectures for the filter banks in speech processor of CI with the following features like minimized area of the filter, reduced power consumption of the speech processor and enhanced presentation of the filter. This paper involves the design and hardware implementation of narrow band pass FIR filter for speech processor of CI using the Xilinx System Generator (XSG) tool on Virtex 7 FPGA.