{"title":"用于PDP扫描驱动IC的高性价比VDMOS","authors":"Xiao-ming Li, Yi-qi Zhuang","doi":"10.1109/ICASIC.2007.4415735","DOIUrl":null,"url":null,"abstract":"VDMOS integrated in scan driver chip for plasma display panels (PDP) is disclosed in the paper, which is based on the epitaxial Bipolar-CMOS- DMOS (BCD) process. The key considerations during the design are proposed here, and abundance simulation and process regulation is done on the structure and parameter optimization, by the testing on the VDMOS parameter and chip parameter, the results is favorable for 170 V PDP scan driver chip, which contributes to the competitive cost efficiency.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Cost-effective VDMOS for PDP scan driver IC\",\"authors\":\"Xiao-ming Li, Yi-qi Zhuang\",\"doi\":\"10.1109/ICASIC.2007.4415735\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"VDMOS integrated in scan driver chip for plasma display panels (PDP) is disclosed in the paper, which is based on the epitaxial Bipolar-CMOS- DMOS (BCD) process. The key considerations during the design are proposed here, and abundance simulation and process regulation is done on the structure and parameter optimization, by the testing on the VDMOS parameter and chip parameter, the results is favorable for 170 V PDP scan driver chip, which contributes to the competitive cost efficiency.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415735\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415735","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
基于外延双极cmos - DMOS (BCD)工艺，将VDMOS集成在等离子体显示面板(PDP)扫描驱动芯片中。提出了设计过程中的关键考虑因素，并对结构和参数优化进行了大量的仿真和工艺调整，通过对VDMOS参数和芯片参数的测试，结果表明该芯片适合170 V PDP扫描驱动芯片，具有较强的成本效益。
VDMOS integrated in scan driver chip for plasma display panels (PDP) is disclosed in the paper, which is based on the epitaxial Bipolar-CMOS- DMOS (BCD) process. The key considerations during the design are proposed here, and abundance simulation and process regulation is done on the structure and parameter optimization, by the testing on the VDMOS parameter and chip parameter, the results is favorable for 170 V PDP scan driver chip, which contributes to the competitive cost efficiency.
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