利用连通性和频谱方法表征时序逻辑电路的结构

Enrico Macii, Massimo Poncino
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引用次数: 0

摘要

用有限状态机表示有限状态系统是VLSI电路设计中常用的一种方法。基于bdd的算法使得具有非常大状态空间的fsm操作成为可能;然而,当可达状态集的表示增长太多时,原始FSM不再作为一个整体进行管理,需要将其分解为更小的子机器。通过对提取FSM的电路进行结构分析,可以非常有效地确定良好的状态变量分区,从而对逻辑综合和形式化验证应用进行FSM分解。在本文中,我们提出了基于状态机的连通性和频谱特征的FSM分析技术,该技术考虑了状态变量的相互依赖性,但不再依赖于底层电路的结构;因此,它们可以在不同于顺序逻辑优化和FSM验证的上下文中使用。给出了mcnc'91 FSM基准和iscas'89顺序电路的实验结果并进行了讨论。
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Using connectivity and spectral methods to characterize the structure of sequential logic circuits

Representing finite state systems by means of finite state machines is a common approach in VLSI circuit design. BDD-based algorithms have made possible the manipulation of FSMs with very large state spaces; however, when the representation of the set of reachable states grows too much, the original FSM is no longer manageable as a whole, and it needs to be decomposed into smaller sub-machines. Structural analysis of the circuit from which the FSM has been extracted has shown to be very effective to determine good state variable partitions which induce FSM decomposition for logic synthesis and formal verification applications. In this paper we propose FSM analysis techniques based on connectivity and spectral characteristics of the state machine which take into account the mutual dependency of the state variables, but which are no longer dependent on the structure of the underlying circuit; therefore, they may be used in a context different from sequential logic optimization and FSM verification. Experimental results are presented and discussed for the mcnc'91 FSM benchmarks and for the iscas'89 sequential circuits.

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