Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture

Phase frequency detector is one of the basic building blocks for Phase Locked Loop (PLL) architecture. The power efficient Delay flip-flop based Phase frequency detector topology is proposed with two parallel clocked latches by following twin latch parallel paradigm method. To construct the latching sections of the circuit, the power reduction techniques such as reducing the numbers of transistors and spilt path technique are incorporated, which leads to reduction of dynamic power and short circuit power consumption respectively. The twin latch paradigm method improves the performance of the system interms of speed due to the sampling of input data at both positive and negative edge arrival of the clock signal. The proposed topology is implemented in MICROWIND EDA tool and evaluated by simulating the circuit under 0.12µm CMOS process technology. The simulation infers that the proposed design achieves power saving from 28.57% to 33.82%, improvement of power energy product ( PEP) from 0.6% to 2.5% and Power area product (PAP) from 10.66% to 12.6% compared to conventional phase frequency detectors.