2.5 gb /s 0.13 μm CMOS电流模逻辑收发器

Zhenyu Zhao, Jianjun Wang, Shaoqing Li, Jihua Chen
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引用次数: 8

摘要

采用0.13 μ m CMOS技术实现了2.5 gb /s电流模逻辑(CML)收发器,实现了芯片间串行互连。为了补偿信道衰减和其他损害,在发射机和接收机上都包括了预强调电路和均衡器。通过使用有源电感器代替在线螺旋电感器,实现了6ghz 3db带宽。输出和输入缓冲器采用直流偏置补偿电路,以保持共模电压稳定。布局仿真验证了该收发器的有效性。该收发器在2.5v电源下仅消耗160兆瓦的功率。发射器和接收器的模具面积分别为0.015 mm2和0.01 mm2。收发器工作速度为2.5 gb /s,接收灵敏度为100mv。
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A 2.5-Gb/s 0.13-μm CMOS current mode logic transceiver with pre-emphasis and equalization
A 2.5-Gb/s current-mode logic (CML) transceiver is implemented in 0.13 - mum CMOS technology for serial inter-chip interconnection. To compensate the channel attenuation and other impairments, pre-emphasis circuit is included at the transmitter and equalizer at the receiver. 6-GHz 3 dB bandwidth is achieved through the use of active inductors instead of online spiral inductors. DC offset compensate circuits are employed in the output and input buffers to keep the common mode voltage stable. Layout simulation demonstrates the effectiveness of the transceiver. This transceiver consumes only 160 mw of power with 2.5v power supply. The die area of transmitter and receiver are 0.015 mm2, 0.01 mm2 respectively. The transceiver can be operated at 2.5-Gb/s with 100 mv receiver sensitivity.
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