{"title":"一种13nV/✓Hz 4.5μW斩波仪表放大器，具有鲁棒纹波抑制和输入阻抗增强技术","authors":"Liang Fang, P. Gui","doi":"10.1109/CICC48029.2020.9075876","DOIUrl":null,"url":null,"abstract":"This paper presents a 13n V /✓Hz Capacitively-coupled Chopper Instrumentation Amplifier (CCIA) implemented in 180nm CMOS. Two new techniques are proposed to address two known drawbacks of CCIAs, chopping ripple and limited input impedance. An improved dynamic offset zeroing (iDOZ) is proposed to suppress the chopping ripple to a mean value of 300μ V and a standard deviation of 500μV, with negligible power, area and noise overhead. A highly-linear three-terminal varactor is proposed in the positive feedback loop of the CCIA to boost the input impedance by 1000 times. This design consumes 4.5 μW power and achieves a noise efficiency factor of 1.3 and a power efficiency factor of 1.1.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 13nV/✓Hz 4.5μW Chopper Instrumentation Amplifier with Robust Ripple Reduction and Input Impedance Boosting Techniques\",\"authors\":\"Liang Fang, P. Gui\",\"doi\":\"10.1109/CICC48029.2020.9075876\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 13n V /✓Hz Capacitively-coupled Chopper Instrumentation Amplifier (CCIA) implemented in 180nm CMOS. Two new techniques are proposed to address two known drawbacks of CCIAs, chopping ripple and limited input impedance. An improved dynamic offset zeroing (iDOZ) is proposed to suppress the chopping ripple to a mean value of 300μ V and a standard deviation of 500μV, with negligible power, area and noise overhead. A highly-linear three-terminal varactor is proposed in the positive feedback loop of the CCIA to boost the input impedance by 1000 times. This design consumes 4.5 μW power and achieves a noise efficiency factor of 1.3 and a power efficiency factor of 1.1.\",\"PeriodicalId\":409525,\"journal\":{\"name\":\"2020 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"98 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC48029.2020.9075876\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC48029.2020.9075876","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
提出了一种采用180nm CMOS实现的13n V /✓Hz电容耦合斩波仪表放大器(CCIA)。提出了两种新技术来解决ccia的两个已知缺点，斩波纹波和有限的输入阻抗。提出了一种改进的动态偏置调零(iDOZ)方法，可将斩波抑制到300μ V的平均值和500μV的标准差，且功率、面积和噪声开销可忽略。在CCIA的正反馈回路中提出了一种高线性三端变容器，将输入阻抗提高了1000倍。本设计功耗为4.5 μW，噪声效率系数为1.3，功率效率系数为1.1。
A 13nV/✓Hz 4.5μW Chopper Instrumentation Amplifier with Robust Ripple Reduction and Input Impedance Boosting Techniques
This paper presents a 13n V /✓Hz Capacitively-coupled Chopper Instrumentation Amplifier (CCIA) implemented in 180nm CMOS. Two new techniques are proposed to address two known drawbacks of CCIAs, chopping ripple and limited input impedance. An improved dynamic offset zeroing (iDOZ) is proposed to suppress the chopping ripple to a mean value of 300μ V and a standard deviation of 500μV, with negligible power, area and noise overhead. A highly-linear three-terminal varactor is proposed in the positive feedback loop of the CCIA to boost the input impedance by 1000 times. This design consumes 4.5 μW power and achieves a noise efficiency factor of 1.3 and a power efficiency factor of 1.1.
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