用于高精度全差分开关电容读出电路的多相时钟发生器

X. Lai, Kaipei Zhang, Chen Liu, Yuheng Wang, Longjie Zhong, Jiangtao Wang, Qiang Ye, Dejun Ma
{"title":"用于高精度全差分开关电容读出电路的多相时钟发生器","authors":"X. Lai, Kaipei Zhang, Chen Liu, Yuheng Wang, Longjie Zhong, Jiangtao Wang, Qiang Ye, Dejun Ma","doi":"10.1109/EDSSC.2017.8126559","DOIUrl":null,"url":null,"abstract":"In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks, and is driven by these clocks. The influence of charge injection of readout is reduced and thus its accuracy is improved. For more complex switched capacitor circuits, functional extension can be achieved only with logical combination. This generator is stimulated in a commercial 180nm CMOS process in SPICE. The simulation results show that accuracy of SC circuit is increased by 8.5%.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit\",\"authors\":\"X. Lai, Kaipei Zhang, Chen Liu, Yuheng Wang, Longjie Zhong, Jiangtao Wang, Qiang Ye, Dejun Ma\",\"doi\":\"10.1109/EDSSC.2017.8126559\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks, and is driven by these clocks. The influence of charge injection of readout is reduced and thus its accuracy is improved. For more complex switched capacitor circuits, functional extension can be achieved only with logical combination. This generator is stimulated in a commercial 180nm CMOS process in SPICE. The simulation results show that accuracy of SC circuit is increased by 8.5%.\",\"PeriodicalId\":163598,\"journal\":{\"name\":\"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2017.8126559\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2017.8126559","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了一种应用于微机电系统(MEMS)差动传感器的高精度全差分开关电容读出电路的无重叠时钟(NVC)发生器。与传统的产生一组不重叠时钟的电路相比,该电路产生一组新的时钟,这些时钟嵌套在原有的不重叠时钟中,并由这些时钟驱动。减小了电荷注入对读数的影响,提高了读数的精度。对于更复杂的开关电容电路,只有通过逻辑组合才能实现功能扩展。该发生器在SPICE的商业180nm CMOS工艺中进行了模拟。仿真结果表明,SC电路的精度提高了8.5%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit
In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks, and is driven by these clocks. The influence of charge injection of readout is reduced and thus its accuracy is improved. For more complex switched capacitor circuits, functional extension can be achieved only with logical combination. This generator is stimulated in a commercial 180nm CMOS process in SPICE. The simulation results show that accuracy of SC circuit is increased by 8.5%.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Photocapacitive effect of ferroelectric hafnium-zirconate capacitor structure A new quasi-3-D subthreshold current/swing model for fully-depleted quadruple-gate (FDQG) MOSFETs A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS Improved performance of pentacene OTFT by incorporating Ti in NdON gate dielectric Investigated raman spectroscopy of graphene material properties
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1