Analyze the ATMOS configuration with VTH abolition logic in 4×1 MUX

A speculative configuration of MOS transistors with a threshold rejection technique is modified. The design configuration is analyzed logic in aspect cum internal threshold abolition (ITA) and discloses circuit imminent and recital confines. Consequent circuit equations exemplify the exchange between the voltage drop and the reverse leakage. Moreover, a circuit development process for the improvement of the power transmission efficiency (PTE) of a 4×1 MUX with ITA MOS configuration was modified based on the design. A 4×1 MUX was optimized and employed in a digital system 45-nm CMOS technology, and Cadence simulation experimental implementation results of the leakage power and PCE illustrate superior conformity through the proposed configuration.