L. Song, Y. Liang, H. Onoda, C. W. Lai, T. Wallner, A. Pofelski, C. Gruensfelder, E. Josse, T. Okawa, J. Brown, R. Williams, J. Holt, J. W. Weijtmans, B. Greene, H. Utomo, S. Lee, D. Nair, Q. Zhang, C. Zhu, X. Wu, M. Sherony, Y. Lee, W. Henson, R. Divakaruni, E. Kaste
{"title":"PMOSFET布局依赖于嵌入式SiGe源/漏极在POLY和STI边缘在32/28nm CMOS技术","authors":"L. Song, Y. Liang, H. Onoda, C. W. Lai, T. Wallner, A. Pofelski, C. Gruensfelder, E. Josse, T. Okawa, J. Brown, R. Williams, J. Holt, J. W. Weijtmans, B. Greene, H. Utomo, S. Lee, D. Nair, Q. Zhang, C. Zhu, X. Wu, M. Sherony, Y. Lee, W. Henson, R. Divakaruni, E. Kaste","doi":"10.1109/VLSI-TSA.2012.6210152","DOIUrl":null,"url":null,"abstract":"The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology\",\"authors\":\"L. Song, Y. Liang, H. Onoda, C. W. Lai, T. Wallner, A. Pofelski, C. Gruensfelder, E. Josse, T. Okawa, J. Brown, R. Williams, J. Holt, J. W. Weijtmans, B. Greene, H. Utomo, S. Lee, D. Nair, Q. Zhang, C. Zhu, X. Wu, M. Sherony, Y. Lee, W. Henson, R. Divakaruni, E. Kaste\",\"doi\":\"10.1109/VLSI-TSA.2012.6210152\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.\",\"PeriodicalId\":388574,\"journal\":{\"name\":\"Proceedings of Technical Program of 2012 VLSI Technology, System and Application\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Technical Program of 2012 VLSI Technology, System and Application\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2012.6210152\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2012.6210152","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology
The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.
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