具有减小偏移和增益误差的单位增益缓冲器

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320831

Guangmao Xing, S. Lewis, T. R. Viswanathan

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引用次数: 5

摘要

采用0.35 μ m CMOS技术制备了单位增益缓冲器。该电路在级联源跟随电路中使用前馈和局部反馈以及两个全局反馈回路:一个回路用于减小输出电阻、增益误差和偏置，另一个回路用于进一步减小增益误差。该缓冲器在3.3 V时消耗3.7 mW，在驱动13-pF容性负载时带宽为92 MHz

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A Unity-Gain Buffer with Reduced Offset and Gain Error

A unity-gain buffer has been fabricated in 0.35-mum CMOS technology. The circuit uses feed forward and local feedback in a cascaded source follower circuit as well as two global feedback loops: one to reduce the output resistance, gain error, and offset and a second loop to further reduce gain error. The buffer consumes 3.7 mW at 3.3 V and has a bandwidth of 92 MHz when driving a 13-pF capacitive load

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IEEE Custom Integrated Circuits Conference 2006

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