高效的数字图像解码器硬件实现

2017 25th Telecommunication Forum (TELFOR) Pub Date : 2017-11-01 DOI:10.1109/TELFOR.2017.8249403

Goran Savic, M. Prokin, V. Rajovic, D. Prokin

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引用次数: 1

摘要

本文描述了一种高效的数字图像解码器的硬件实现。所提出的图像解码器由每个块(熵解码器、解码器概率估计器、去量化器和逆子带变压器)组成，旨在优化硬件架构，减少单独块本身以及整个图像解码器中使用的逻辑和内存资源的数量。通过在低成本FPGA芯片上的实现验证了所提出的实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Efficient hardware realization of digital image decoder

In this paper, efficient hardware realization of digital image decoder, has been described. Each block, the proposed image decoder consists of (entropy decoder, decoder probability estimator, dequantizer and inverse subband transformer), has been developed with intention to optimize the hardware architecture and reduce the amount of used logic and memory resources in separate blocks themselves, as well as in the entire image decoder. The proposed realization has been verified by implementation within a low cost FPGA chip.

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2017 25th Telecommunication Forum (TELFOR)

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