216GHz 0.5mW发射机,采用65nm CMOS,采用紧凑型功率组合器

Sriram Muralidharan, Kefei Wu, M. Hella
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引用次数: 6

摘要

本文介绍了一种采用65nm块体CMOS工艺的216GHz, 0.5mW发射机的设计和测量。发射器由放大器-乘法器链组成,其中功率放大器在110GHz向无源倍频器提供Psat =16dBm。PA级采用基于垂直耦合传输线的新型单端到2路差分功率组合器。采用MOS变容管实现的无源倍频器紧随PA之后。216GHz发射机在216GHz时的最大输出功率为0.5mW,带宽为2.8%,而1V直流电源的功耗为500mW。该芯片采用薄BEOL七金属ST-65nm CMOS工艺实现,总面积为0.88mm2。
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A 216GHz 0.5mW transmitter with a compact power combiner in 65nm CMOS
This paper presents the design and measurements of a 216GHz, 0.5mW transmitter using 65nm bulk CMOS process. The transmitter is formed of an amplifier-multiplier chain, where the power amplifier delivers a Psat =16dBm at 110GHz to a passive frequency doubler. The PA stage employs a novel single-ended to 2-way differential power combiner based on vertically coupled transmission lines. A passive frequency doubler implemented using MOS varactors follows the PA. The 216GHz transmitter delivers a maximum of 0.5mW at 216GHz with a 2.8% bandwidth, while consuming 500mW from a 1V DC supply. The chip, implemented in thin BEOL seven metal ST-65nm CMOS process, occupies a total area of 0.88mm2.
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