基于高阻抗点支路的“折叠”级联码在温度和辐射效应方面提高零电平模拟电路稳定性的方法

N. Prokopenko, A. I. Serebryakov, N. Butyrlagin
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引用次数: 2

摘要

本文考虑了基于具有小零电平(偏置电压,Vov)及其在温度和辐射效应方面漂移的经典“折叠”级联码的双极模拟集成电路的结构和原理图合成问题。因此,该方案的现代化基础采用了著名的基本模拟IC(运算放大器,连续稳定器,电压比较器等),其中我们根据以下规则引入一些结构冗余,以提供降低Vov及其电压漂移效应在一个或两个数量级)。
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A method of increasing the stability of the zero level analog circuits based on the “Folded” cascode with the high-impedance point branch in the terms of temperature and radiation effects
It is considered the problem of synthesis of structural and schematics of bipolar analog ICs based on the classic “folded” cascode which have a small zero-level (offset voltage, Vov) and its drift in the terms of temperature and radiation effects. Thus the basis of the modernization of the scheme are adopted by well-known basic analog IC (operational amplifiers, continuous stabilizers, voltage comparators, etc.), in which by the rules set forth below, we introduce some structural redundancy, which provides a decrease Vov and its voltage drift effect on one or two orders).
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