Improved $\pi$-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver

The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM based receivers. In this framework, a HR-NPM architecture has been discussed based on the π-delayed driving signals. The harmonic rejection and the system complexity have been improved with this new architecture such that the Harmonic rejection achieved by this structure is the same of the conventional HR-2NPM and the system complexity has been reduced by half, where as the number of the gain stages and the switches has been reduced. In this context, a 5-path mixer is thus proposed. It allows rejecting up to the 8th harmonic with only 2 differential gain stages by appropriately implementing the switches whereas only the 6th harmonic would be rejected with conventional HR-8PM topologies having 3 amplifier stages. Our structure shows high resilience to clocks overlapping effects.