Variation tolerant digitally assisted high-speed IO PHY

Technology scaling leads to reduction of supply voltage and increase in random device variability and thus creates new challenges for analog design. A complete overhaul of the design approach at system architecture and circuit topology levels is necessary to keep the link robust and tolerant to low supply voltage and random variability challenges. This paper presents key analog circuit architecture techniques employed to implement 6.4GT/s per lane, 14mW/Gbps analog front end high-speed IO interfaces on Poulson — a 32nm next generation Intel Itanium microprocessor [1].