Challenges in microprocessor physical and power management design

The free ride from process technology for CPU design has ended. Innovations in architecture, circuit design, and physical implementation are required to cope with increased challenges imposed by the lack of process scaling, increased variability and layout-dependent effects. In addition, power density is rising to prohibitive levels and has now become the predominant performance limiter. Extensive power management at both architectural and circuit levels is a major focus point in today's microprocessor design. This paper will give an overview of the issues, the potential solutions and the tool requirements to address the ever- increasing physical design and power management challenges.