{"title":"一种电压可扩展的先进DFM RAM,用于低功耗SoC平台的加速筛选","authors":"H. Shimano, F. Morishita, K. Dosaka, K. Arimoto","doi":"10.1093/ietele/e90-c.10.1927","DOIUrl":null,"url":null,"abstract":"The advanced-DFM RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability(@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 cell/bit with the complementary dynamic memory operation and has the 1 cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (sense synchronized write) peripheral circuit technologies are also adopted for the low voltage and FV controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform\",\"authors\":\"H. Shimano, F. Morishita, K. Dosaka, K. Arimoto\",\"doi\":\"10.1093/ietele/e90-c.10.1927\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The advanced-DFM RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability(@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 cell/bit with the complementary dynamic memory operation and has the 1 cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (sense synchronized write) peripheral circuit technologies are also adopted for the low voltage and FV controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.\",\"PeriodicalId\":142478,\"journal\":{\"name\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1093/ietele/e90-c.10.1927\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1093/ietele/e90-c.10.1927","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform
The advanced-DFM RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability(@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 cell/bit with the complementary dynamic memory operation and has the 1 cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (sense synchronized write) peripheral circuit technologies are also adopted for the low voltage and FV controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.